1. Field of the Invention
The present invention relates to an MSK signal demodulating circuit for demodulating an MSK (Minimum Shift Keying) signal.
2. Description of the Related Art
One of the digital modulation systems recently adopted in radiocommunication is MSK modulation system which means a continued phase FSK (Frequency Shift Keying) system having a modulation index of 0.5, transmitting a mark frequency (fm) and a space frequency (fs) in response to transmission data 1, 0. The MSK modulation system has an advantage of resisting non-linear distortion because of constant amplitude in modulation carrier. A conventional method for demodulating an MSK signal typically involves orthogonal synchronous detection by reproducing a carrier synchronized in phase with a carrier f0 at the sending end.
FIG. 4 is a block diagram showing a conventional MSK signal demodulating circuit by means of such method. In this drawing, an MSK signal inputted to an input terminal 10 is subject to orthogonal synchronous detection by detectors 12 and 13 on the basis of an output signal of a carrier reproducing circuit 21, which reproduces a carrier phase-synchronized with carrier f0 at the sending end, and of another signal which is 90.degree. phase-shifted from the said signal by 90.degree. phase shifter 14. Then, the bands of the detected analog signals are limited by low-pass filters 15 and 16 respectively, followed by conversion of the respective analog signals into digital ones by identification circuits 17 and 18. While the clock reproduced by a clock reproducing circuit 30 is subject to 1/2 frequency demultiplication by a 1/2 divider 31 to use it as a timing pulse for the identification circuits 17 and 18 in which A/D converters are used in general.
Such a demodulation system is called a parallel demodulation system in view of the separate detections for a common component (axis I) and an orthogonal component (axis Q). Data I and Q converted into digital signals are inputted to an error correcting circuit 40 for error correction, and then outputted from an output terminal 50. Error correction codes are used in general to assure high quality of transmission performance, while the error correcting circuit 40 is often provided as an LSI. For example, in case of using a convolutional code as an error correction code, the error correcting circuit 40 is provided as Viterbi decoding LSI which receives data I and Q.
The above MSK demodulation system is on a parallel demodulation basis, requiring an identification circuit, each for axis I and axis Q, while such a type of circuit is expensive in general, resulting in higher costs.
On the other hand, in using an A/D converter for an identification circuit, an AGC (automatic gain control) amplifier is often installed at the front of the A/D converter in order to prevent the error rate from being degraded by variation in input level of the A/D converter, while an AGC amplifier is needed each for axis I and axis Q also in this case, complicating the construction and resulting in higher costs again.
Moreover, to make a dual system, the identification circuits of axis I and axis Q are required to have the same identification performance, while it is actually pretty difficult to mass-produce such circuits working stably over the whole range of operating temperature.